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FlashFlex51 MCU
SST89C54 / SST89C58
SST89C5xFlashFlex51 MCU
Data Sheet
FEATURES:
* 8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory - Fully Software Compatible - Development Toolset Compatible - Pin-For-Pin Package Compatible * SST89C54/58 Operation - 0 to 33MHz at 5V * 256 Bytes Internal RAM * Dual Block SuperFlash EEPROM - SST89C58: 32 KByte primary block (128-Byte sector size) + 4 KByte secondary block (64-Byte sector size) - SST89C54: 16 KByte primary block (128-Byte sector size) + 4 KByte secondary block (64-Byte sector size) - Individual Block Security Lock with SoftLock - Concurrent operation during In-Application Programming (IAP) - Memory Re-mapping for Interrupt Support during IAP * Support External Address Range up to 64 KByte of Program and Data Memory * Three High Current Drive Ports (16 mA each) * Three 16-bit Timers/Counters * Full-Duplex Serial Port (UART) * Six Interrupt Sources at 2 Priority Levels * Programmable Watchdog Timer (WDT) * Four 8-bit I/O Ports (32 I/O Pins) * TTL- and CMOS-Compatible Logic Levels * Low Power Modes - Power-down Mode with External Interrupt Wake-up - Standby (Stop Clock) * Low Voltage at 2.7V (0 to 12MHz) * PDIP-40, PLCC-44 and TQFP-44 Packages * Temperature Ranges: - Commercial (0C to +70C) - Industrial (-40C to +85C)
PRODUCT DESCRIPTION
The SST89C54 and SST89C58 are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with the state-of-the-art SuperFlash CMOS semiconductor process technology. The device uses the same 8051 instruction set and is pinfor-pin compatible with standard 8051 microcontroller devices. The device comes with 20/36 KByte of on-chip flash EEPROM program memory using SST's patented and proprietary CMOS SuperFlash EEPROM technology with SST's field-enhancing, tunneling injector, split-gate memory cells. The SuperFlash memory is partitioned into 2 independent program memory blocks. The primary SuperFlash Block 0 occupies 16/32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 4 KByte of internal program memory space. The 4 KByte secondary SuperFlash block can be mapped to the highest or lowest location of the 64 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory. The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST's devices. During the power-on reset, the device can be configured as a slave to an external host for source code storage or as a master to an external host for an in-application programming (IAP) operation. The device
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is designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility. The device is pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the IAP operation. An example of bootstrap loader is available for the user's reference and convenience only. SST does not guarantee the functionality nor the usefulness of the sample bootstrap loader. Chip-Erase operations will erase the pre-programmed sample code. In addition to 20/36 KByte of SuperFlash EEPROM program memory on-chip, the device can address up to 64 KByte of external program memory. In addition to 256 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed. SST's highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs. These advantages translate into significant cost and reliability benefits for our customers.
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
TABLE OF CONTENTS
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Memory Re-mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Data RAM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 External Host Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.0 TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 Hard Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet 10.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 Standby Mode (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.0 CLOCK INPUT OPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.1 Recommended Capacitor Values for Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.2 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3 Flash Memory Programming Timing Diagrams with External Host Mode . . . . . . . . . . . . . . . . . . . . . . 46 13.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
LIST OF FIGURES
FIGURE 2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 2-2: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 2-3: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 3-1: Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FIGURE 3-2: SST89C54 Program Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FIGURE 3-3: SST89C58 Program Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FIGURE 3-4: SST89C54 Re-mapped Program Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIGURE 3-5: SST89C58 Re-mapped Program Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIGURE 4-1: I/O Pin Assignments for External Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FIGURE 7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 8-1: Security Lock Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIGURE 10-1: Power-On Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 11-1: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 12-1: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FIGURE 12-2: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FIGURE 12-3: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 FIGURE 12-4: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 FIGURE 12-5: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FIGURE 12-6: AC Input/Output Test Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FIGURE 12-7: Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FIGURE 12-8: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 12-9: IDD Test Condition, Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 12-10: IDD Test Condition, Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 12-11: IDD Test Condition, Standby (Stop Clock) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 12-12: Read-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FIGURE 12-13: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FIGURE 12-14: Block-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FIGURE 12-15: Sector-Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FIGURE 12-16: Byte-Program; Prog-SB3, Prog-SB2, Prog-SB1, Prog-RB1, and Prog-RB0 . . . . . . . . . . . 48 FIGURE 12-17: Burst-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FIGURE 12-18: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
LIST OF TABLES
TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TABLE 3-1: Re-mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 3-2: FlashFlex51 SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-3: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-4: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-5: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 3-6: Timer/Counters SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TABLE 3-7: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TABLE 4-1: External Host Mode Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 4-2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 4-3: In-Application Programming Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 8-1: Security Lock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 8-2: Security Lock Access Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 10-1: SST89C54/58 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TABLE 11-1: Recommended values for C1 and C2 by crystal type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TABLE 12-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TABLE 12-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 12-3: AC Conditions of Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 12-4: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 12-5: Pin Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 12-6: DC Electrical Characteristics for 33MHz devices; 4.5-5.5V . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 12-7: DC Electrical Characteristics for 12MHz devices; 3.0-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 12-8: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 12-9: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 12-10: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TABLE 12-11: Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
1.0 FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
Oscillator
8051 CPU Core
Interrupt Control
6 Interrupts
Watchdog Timer
FCU
SuperFlash EEPROM Primary Block 16K/32K x81
RAM 256 x8 8 I/O Port 0 I/O 8 Security Lock I/O Port 1 8 I/O Port 2 I/O 8 I/O Port 3 I/O I/O
Secondary Block 4K x8
Timer 0 (16-bit) Timer 1 (16-bit) Timer 2 (16-bit) 8-bit UART
344 ILL B1.2
1. 16K x 8 for SST89C54 32K x 8 for SST89C58 FCU = Flash Control Unit 8051 CPU Core = ALU, ACC, B-Reg., Instruction Reg., PC, Timing and Control, etc.
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
2.0 PIN ASSIGNMENTS
(T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 (WR#) P3.6 (RD#) P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7
40 39 38 37 36 35 34
VDD
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2)
P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
344 40-pdip PI P1.3
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
VDD
P1.4
P1.3
P1.2
P0.1 (AD1)
P0.3 (AD3)
P1.0 (T2)
P0.0 (AD0)
P1.1 (T2EX)
NC
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# NC ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)
40-pin PDIP 8 Top View 33 32 9 10 11 12 13 14 15 16 17 18 19 20 31 30 29 28 27 26 25 24 23 22 21
44-lead TQFP Top View
10
23 11 12 13 14 15 16 17 18 19 20 21 22
(WR#) P3.6
(RD#) P3.7
XTAL2
XTAL1
VSS
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
344 44-tqfp TQJ P2.4
NC = No Connect (Reserved)
FIGURE
2-1: PIN ASSIGNMENTS FOR 40-PIN PDIP
P1.1 (T2EX)
FIGURE
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
2-2: PIN ASSIGNMENTS FOR 44-LEAD TQFP
P1.0 (T2)
P1.4
P1.3
P1.2
6 P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 7 8 9 10 11 12 13 14 15 16
5
4
3
2 1 44 43 42 41 40 39 38 37 36 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# NC ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)
VDD
NC
44-lead PLCC Top View
35 34 33 32 31 30
17 29 18 19 20 21 22 23 24 25 26 27 28 (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (WR#) P3.6 (RD#) P3.7 (A12) P2.4 VSS XTAL2 XTAL1 NC
344 44-plcc NJ P3.3
NC = No Connect (Reserved)
FIGURE
2-3: PIN ASSIGNMENTS FOR 44-LEAD PLCC
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Data Sheet
2.1 Pin Descriptions
TABLE
Symbol P0[7:0]
2-1: PIN DESCRIPTIONS (1 OF 2)
Type1 I/O Name and Functions Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have `1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. In this application it uses strong internal pull-ups when transitioning to `1's. Port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during external host mode verification. External pull-ups are required during program verification or as a general purpose I/ O port.
P1[7:0]
I/O with internal Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 output buffers can pull-ups drive LS TTL inputs. Port 1 pins that have `1's written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (IIL, see Tables 12-6 and 12-7) because of the internal pull-ups. P1[5, 6, 7] have high current drive of 16mA. Port 1 also receives the low-order address bytes during external host mode programming and verification. I I T2: External count input to Timer/Counter 2 T2EX: Timer/Counter 2 capture/reload trigger
P1[0] P1[1] P2[7:0]
I/O with internal Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have `1's pull-ups written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current (IIL, see Tables 12-6 and 12-7) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application it uses strong internal pull-ups when outputting `1's. Port 2 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. I/O with internal Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers pull-ups can drive LS TTL inputs. Port 3 pins that have `1's written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (IIL, see Tables 12-6 and 12-7) because of the internal pull-ups. Port 3 serves the functions of various special features of the device. Port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. I O I I I I O O I/O RXD: UART - Receive input TXD: UART - Transmit output INT0#: External Interrupt 0 input INT1#: External Interrupt 1 input T0: External Count input to Timer/Counter 0 T1: External Count input to Timer/Counter 1 WR#: External Data Memory Write strobe RD#: External Data Memory Read strobe Program Store Enable: PSEN# is the Read strobe to External Program Memory. When the device is executing code from Internal Program Memory, PSEN# is inactive ("H"). When the device is executing code from External Program Memory, PSEN# is activated twice each machine cycle, except that two PSEN# activations are skipped during each access to External Data Memory. While the RST input is continually held high (for more than ten machine cycles), a forced high-to-low input transition on the PSEN# pin will bring the device into the external host mode programming.
P3[7:0]
P3[0] P3[1] P3[2] P3[3] P3[4] P3[5] P3[6] P3[7] PSEN#
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Data Sheet TABLE
Symbol RST
2-1: PIN DESCRIPTIONS (2 OF 2)
Type1 I Name and Functions Reset: A high logic state on this pin for two machine cycles, while the oscillator is running, will reset the device. If the PSEN# pin is driven by a high-to-low input transition while the RST input pin is held high, the device will enter the external host mode. Otherwise, the device will enter the normal operation mode. External Access Enable: EA#2 must be connected to VIL in order to enable the device to fetch code from External Program Memory. EA# must be strapped to VIH for internal program execution. However, security lock level 4 will disable EA#, and program execution is only possible from internal program memory. The EA# pin can tolerate a high voltage3 of 12V (see Electrical Specification, Section 12.0). Address Latch Enable: ALE is the output signal for latching the low byte of the address during an access to external memory. This pin is also the programming pulse input (PROG#) for flash programming. Normally the ALE5 is emitted at a constant rate of 1/6 the crystal frequency and can be used for external timing and clocking. One ALE pulse is skipped during each access to external data memory. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generation circuits. Crystal 2: Output from the inverting oscillator amplifier. Power Supply Ground
T2-1.9 344
EA#
I
ALE/ PROG#4
I/O
XTAL1 XTAL2 VDD VSS
I O I I
1. I = Input; O = Output 2. EA# is not sampled and latched on reset after level 2 or level 3 locked. MCU will jump to run internal code if EA# changes from VIL to VIH. This is a security compromise. Use level 4 lock to fix. 3. It is not necessary to receive a 12V programming supply voltage during flash programming. 4. Applying 10-50 K pull-up resistor to this pin may improve the device's performance. 5. ALE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter into modes other than normal working mode. The solution is to add a pull-up resistor of 3-50 K to VDD, e.g. for ALE pin.
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Data Sheet
3.0 MEMORY ORGANIZATION
The SST89C54/58 has separate address spaces for program and data memory. When internal code operation is enabled (EA# = 1), the primary 16/32 KByte flash memory block is always visible to the program counter for code fetching. Figures 3-2 and 3-3 show the program memory organizations for the SST89C54/58. When internal code operation is enabled (EA# = 1), the secondary 4 KByte flash memory block is selectively visible for code fetching. When bit 7 of the SuperFlash Configuration mailbox register (SFCF[7]), is set, the secondary 4 KByte block will be visible for code fetching. 3.1.1 Code Corruption Due to Brown-out The MCU will still run a user's application code even if the VDD drops down to 2V, far below the minimum working voltage of 2.7V. This can cause the program counter (PC) to get lost and sometimes lead to code corruption. The solution is to use an off-chip voltage supervisory chip to keep the MCU in reset state whenever the VDD drops below 2.7V.
3.1 Program Flash Memory
There are two internal flash memory blocks in the SST89C54/58. The primary flash memory Block 0 has 16/32 KByte and occupies the address space 0000H to 3FFFH/7FFFH. The secondary flash memory Block 1 has 4 KByte and occupies the address space F000H to FFFFH. The 16/32K x8 primary SuperFlash block is organized into 128/256 sectors. Each sector contains 2 rows and each row has 64 Bytes. The 4K x8 secondary SuperFlash block is organized into 64 sectors. Each sector contains 2 rows. Each row contains 32 Bytes. Figure 3-1 shows the sector organization for SST89C54/58.
7FFFH Sector 255 7F80H
FFFFH Sector 63 FFC0H
89C58
4000H 3FFFH Sector 127 3F80H 89C54 007FH Sector 0 0000H Block 0 (16/32 KByte) Primary F000H F03FH Sector 0 Block 1 (4 KByte) Secondary
344 ILL F47.7
FIGURE
3-1: SECTOR ORGANIZATION
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
EA# = 1 & SFCF[7] = 1 FFFFH F000H EFFFH 4 KByte INTERNAL
(Block 1)
EA# = 1 & SFCF[7] = 0 FFFFH FFFFH
EA# = 0
48 KByte EXTERNAL 44 KByte EXTERNAL
64 KByte EXTERNAL
4000H 3FFFH 16 KByte INTERNAL
(Block 0)
4000H 3FFFH 16 KByte INTERNAL
(Block 0)
0000H
0000H
0000H
344 ILL F21.2
FIGURE
3-2: SST89C54 PROGRAM MEMORY ORGANIZATION
EA# = 1 & SFCF[7] = 1 FFFFH F000H EFFFH 4 KByte INTERNAL
(Block 1)
EA# = 1 & SFCF[7] = 0 FFFFH FFFFH
EA# = 0
32 KByte EXTERNAL 28 KByte EXTERNAL 64 KByte EXTERNAL
8000H 7FFFH
8000H 7FFFH
32 KByte INTERNAL
(Block 0)
32 KByte INTERNAL
(Block 0)
0000H
0000H
0000H
344 ILL F11.2
FIGURE
3-3: SST89C58 PROGRAM MEMORY ORGANIZATION
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Data Sheet
3.2 Memory Re-mapping
The SST89C54/58 memory re-mapping feature allows users to re-map the secondary flash memory block physical address to overlay the lower order logical address so that interrupts can be serviced when the primary flash memory block (Block 0) is busy under Program/Erase operation. Since Block 0 occupies the low order program address space of the 8051 architecture where the interrupt vectors reside, those interrupt vectors will normally not be available when Block 0 is being programmed. SST89C54/58 provides four options of memory re-mapping (Refer to Table 3-1). When the lowest 4 KByte are remapped, any program access within logical address range 0000H-0FFFH will have the 4 most significant address bits forced to "1", redirecting the access to F000H-FFFFH. Note that the physical contents of the overlaid portion of Block 0 (i.e. physical locations 0000H-0FFFH in the current example) will not be addressable by the program counter, but only accessible through IAP registers. Block 1 is still accessible through F000H-FFFFH. Block 1 is addressable by the program counter in both logical address ranges 0000H0FFFH and F000H-FFFFH.
3.2.1 Activation and Deactivation of Memory Re-mapping The actual amount of memory that is re-mapped is controlled by Map-En[1:0] bits as shown in Table 3-1. The MapEn[1:0] bits are the same bits as SFCF[1:0]. The MapEn[1:0] bits are under software control and can be changed during program execution. Since changing re-mapping will cause program re-location, it is advisable that the instruction that changes the Map-En[1:0] be in the portion of memory that is not affected by the re-mapping change. (See Figures 3-4 and 3-5 and the application note, Memory Re-Mapping of the SST89C54/58 Microcontroller). The Map-En[1:0] bits are initialized at Reset according to the contents of two non-volatile register bits, Re-Map[1:0]. The Re-Map[1:0] bits are programmed via PROG_RB1 and PROG_RB0 external host mode and IAP commands. Refer to "External Host Programming Mode" in Section 4.1 or IAP section for description. The contents of Map-En[1:0] are only updated according to Re-Map[1:0] on a successful reset. Any subsequent alteration to the Re-Map[1:0] bits will not automatically change the Map-En[1:0] bits without a reset. Similarly, changes to Map-En[1:0] during program execution will not change ReMap[1:0] bits. To deactivate memory re-mapping, a Chip-Erase operation will revert Re-Map[1:0] to the default status of "11", disabling re-map. Programming 00b to Map-En register also deactivates memory re-mapping, during the run time.
TABLE
11 10 01 00
3-1: RE-MAPPING TABLE
Map-En2,3 00 01 10 11 Comments Re-mapping is turned off. Program memory is in normal configuration. 1 KByte of flash memory location is re-mapped. Program access to location 0000H-03FFH is redirected to F000H-F3FFH. 2 KByte of flash memory location are re-mapped. Program access to location 0000H-07FFH is redirected to F000H-F7FFH. 4 KByte of flash memory location is re-mapped. Program access to location 0000H-0FFFH is redirected to F000H-FFFFH.
T3-1.4 344
RE-MAP[1:0]1
1. Map-En[1:0] are nonvolatile registers which are examined only during Reset. 2. Map-En[1:0] are initialized according to RE-MAP[1:0] during Reset. 3. Map-En[1:0] are located in SFCF[1:0], they determine the re-mapping configuration. They may be changed by the program at run time.
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Data Sheet
EA# = 1 & SFCF[7] = X SFCF [1:0] = 01/10/11 FFFFH
EA# = 1 & SFCF[1] = X SFCF [1:0] = 01/10/11 FFFFH
4 KByte Internal
(Block 1) F000H EFFFH
4 KByte Internal
(Block 1)
F000H EFFFH
28 KByte External
44 KByte External
8000H 7FFFH 4000H 3FFFH
15/14/12 KByte Internal
(Block 0)
31/30/28 KByte Internal
(Block 0)
1/2/4 KByte Internal
0000H (Block 1)
344 ILL F35.5
1/2/4 KByte Internal
0000H (Block 1)
344 ILL F36.3
FIGURE
3-4: SST89C54 RE-MAPPED PROGRAM MEMORY ORGANIZATION
FIGURE
3-5: SST89C58 RE-MAPPED PROGRAM MEMORY ORGANIZATION
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Data Sheet
3.3 Data RAM Memory
SST89C54/58 have 256 Bytes x8 bits internal RAM and can address up to 64 KByte of external data memory.
3.4 Special Function Registers
Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the FlashFlex51 SFR memory map shown below. Individual descriptions of each SFR are provided and Reset values indicated in Tables 3-3 to 3-7. TABLE
F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H PSW1 T2CON1 WDTC1 IP1 P31 IE1 P21 SCON1 P11 TCON1 P01 TMOD SP TL0 DPL TL1 DPH TH0 TH1 WDTD PCON SBUF SFCF SFCM SFAL SFAH SFDT SFST RCAP2L RCAP2H TL2 TH2 ACC1 B1
3-2: FLASHFLEX51 SFR MEMORY MAP
8 BYTES FFH F7H EFH E7H DFH D7H CFH C7H BFH B7H AFH A7H 9FH 97H 8FH 87H
T3-2.1 344
1. SFRs are bit addressable.
3.4.1 SST89C54/58 Special Function Registers TABLE
Symbol ACC1 B* PSW* SP DPL DPH IE* IP* PCON
3-3: CPU
RELATED
SFRS
Direct Address E0H F0H D0H 81H 82H 83H A8H B8H 87H EA SMOD ET2 PT2 CY AC F0 Bit Address, Symbol, or Alternative Port Function MSB ACC[7:0] B[7:0] RS1 RS0 OV F1 P SP[7:0] DPL[7:0] DPH[7:0] ES PS ET1 PT1 GF1 EX1 PX1 GF0 ET0 PT0 PD EX0 PX0 LSB RESET Value 00H 00H 00H 07H 00H 00H 00H xx000000b 0xxx0000b
T3-3.6 344
Description Accumulator B Register Program Status Word Stack Pointer Data Pointer Low Data Pointer High Interrupt Enable Interrupt Priority Power Control
1. Bit Addressable SFRs
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Data Sheet TABLE 3-4: FLASH MEMORY PROGRAMMING SFRS
Direct Address B1H B2H B3H B4H B5H B6H SB[2:0] Bit Address, Symbol, or Alternative Port Function MSB VIS FIE IAPEN FCM LSB Map-En RESET Value 00xxxxxxb 00H 00H 00H 00H xxxx00xxb
T3-4.7 344
Symbol Description SFCF SFCM SFAL SFAH SFDT SFST SuperFlash Configuration SuperFlash Command SuperFlash Address Low SuperFlash Address High SuperFlash Data SuperFlash Status
SuperFlash Low Order Byte Address Register - A7 to A0 (SFAL) SuperFlash High Order Byte Address Register - A15 to A8 (SFAH) SuperFlash Data Register BUSY Flash_busy
SuperFlash Configuration Register (SFCF)
Location B1H 7 VIS 6 IAPEN 5 4 3 2 1
Map-En1
0
Map-En0
Reset Value 00xxxxxxb
Symbol VIS
Function Upper flash block visibility. 1: 4 KByte flash block visible from F000H-FFFFH. 0: 4 KByte flash block not visible. The VIS bit is ignored when re-map is in effect: The VIS bit is "don't care" after re-mapped 1KB, 2KB or 4KB. VIS controls the visibility of Block 1 to program counter (PC) only when re-map is 0 KByte. Enable IAP operation. 1: IAP commands are enabled. 0: IAP commands are disabled. Map enable bit 1. Map enable bit 0. Map-En[1:0] are initialized to default value according to RE-MAP[1:0] during Reset. Refer to Table 3-1.
IAPEN
Map-En1 Map-En0
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Data Sheet SuperFlash Command Register (SFCM)
Location B2H 7 FIE 6 FCM6 5 FCM5 4 FCM4 3 FCM3 2 FCM2 1 FCM1 0 FCM0 Reset Value 00000000b
Symbol FIE
Function Flash Interrupt Enable. 1: INT1# is re-assigned to signal IAP operation completion. External INT1# interrupts are ignored. 0: INT1# is not reassigned. Flash operation command. 000_0001b Chip-Erase 000_0110b Burst-Program 000_1011b Sector-Erase 000_1100b Byte-Verify1 000_1101b Block-Erase 000_1110b Byte-Program 000_1111b Prog-SB12 000_0011b Prog-SB22 000_0101b Prog-SB32 000_1000b Prog-RB02 000_1001b Prog-RB12 All other combinations are not implemented, and reserved for future use.
1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE. 2. These commands must reside in Block 0 (32 KByte Block) only or external code memory.
FCM[6:0]
SuperFlash Address Register (SFAL)
Location B3H 7 6 5 4 3 2 1 0 Reset Value 00000000b SuperFlash Low Order Byte Address Register
Symbol SFAL
Function Mailbox register for interfacing with flash memory block. (Low order address register).
SuperFlash Address Register (SFAH)
Location B4H 7 6 5 4 3 2 1 0 Reset Value 00000000b SuperFlash High Order Byte Address Register
Symbol SFAH
Function Mailbox register for interfacing with flash memory block. (High order address register).
SuperFlash Data Register (SFDT)
Location B5H 7 6 5 4 3 2 1 0 Reset Value 00000000b SuperFlash Data Register
Symbol SFDT
Function Mailbox register for interfacing with flash memory block. (Data register).
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Data Sheet SuperFlash Status Register (SFST) (Read Only Register)
Location B6H 7 SB1 6 SB2 5 SB3 4 3 Busy 2
Flash_busy
1 -
0 -
Reset Value xxxx00xxb
Symbol SB1 SB2 SB3 BUSY
Function Security bit 1. Security bit 2. Security bit 3. Please refer to Table 8-1 for security lock options. Burst-Program completion polling bit. 1: Device is busy with flash operation. 0: Device is available for next Burst-Program operation. Flash operation completion polling bit. 1: Device is busy with flash operation. 0: Device has fully completed the last command, including Burst-Program.
Flash_busy
TABLE
WDTC1 WDTD
3-5: WATCHDOG TIMER SFRS
Watchdog Timer Control Watchdog Timer Data/Reload C0H 86H WDRE WDTS WDT SWDT X0H 00H
T3-5.3 344
1. Bit Addressable SFRs
Watchdog Timer Control Register (WDTC)
Location C0H 7 6 5 4 3 2 1 0 Reset Value
WDRE
WDTS
WDT
SWDT
xxxx0000b
Symbol WDRE
Function Watchdog timer reset enable. 1: Enable watchdog timer reset. 0: Disable watchdog timer reset. Watchdog timer reset flag. 1: Hardware sets the flag on watchdog overflow. 0: External hardware reset clears the flag. Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of watchdog timer overflow. Watchdog timer refresh. 1: Software sets the bit to force a watchdog timer refresh. 0: Hardware resets the bit when refresh is done. Start watchdog timer. 1: Start WDT. 0: Stop WDT.
WDTS
WDT
SWDT
Watchdog Timer Data/Reload Register (WDTD)
Location 7 6 5 4 3 2 1 0 Reset Value
86H Symbol WDTD Function
Watchdog Timer Data/Reload
00000000b
Initial/Reload value in Watchdog Timer, new value won't be effective until WDT is set.
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Data Sheet TABLE
TMOD TCON1 TH0 TL0 TH1 TL1 T2CON1 TH2 TL2 RCAP2H RCAP2L
3-6: TIMER/COUNTERS SFRS
Timer/Counter Mode Control Timer/Counter Control Timer 0 MSB Timer 0 LSB Timer 1 MSB Timer 1 LSB Timer / Counter 2 Control Timer 2 MSB Timer 2 LSB Timer 2 Capture MSB Timer 2 Capture LSB 89H GATE 88H 8CH 8AH 8DH 8BH C8H CDH CCH CBH CAH TF2 EXF2 RCLK TF1 Timer 1 C/T# TR1 M1 TF0 M0 TR0 GATE IE1 TH0[7:0] TL0[7:0] TH1[7:0] TL1[7:0] TCLK EXEN2 TR2 C/T2# CP/RL2# IT1 Timer 0 C/T# M1 IE0 M0 IT0 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
T3-6.1 344
00H
TH2[7:0] TL2[7:0] RCAP2H[7:0] RCAP2L[7:0]
1. Bit Addressable SFRs Note: T2MOD register is not implemented.
TABLE
SBUF SCON1 P01 P11 P21 P31
3-7: INTERFACE SFRS
Serial Data Buffer Serial Port Control Port 0 Port 1 Port 2 Port 3 99H 98H 80H 90H A0H B0H RD# WR# T1 T0 SM0 SM1 SM2 SBUF[7:0] REN TB8 P0[7:0] P2[7:0] INT1# INT0# TXD RXD T2 EX T2 RB8 TI RI Indeterminate 00H FFH FFH FFH FFH
T3-7.5 344
1. Bit Addressable SFRs
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Data Sheet
4.0 FLASH MEMORY PROGRAMMING
The SST89C54/58 internal flash memory can be programmed or erased using the following two methods: * * External host mode In-Application Programming (IAP) mode the non-multiplexed upper order address bus signals for the internal flash memory (A13-A8) along with two of the Port 3 pins (P3[5] as A15 and P3[4] as A14). Two upper order Port 2 pins (P2[7] and P2[6]) and two upper order Port 3 pins (P3[7] and P3[6]) along with RST, PSEN#, ALE/ PROG#, EA# pins are assigned as the control signal pins. The Port 3 pin (P3[3]) is assigned to be the ready/busy status signal, which can be used for handshaking with the external host during a flash memory programming operation. The flash memory programming operation (Erase, Program, Verify, etc.) is internally self-timed. The insertion of an "arming" command prior to entering the external host mode by utilizing the Read-ID operation provides additional protection for inadvertent writes to the internal flash memory caused by a noisy or unstable system environment during power-up or brown-out conditions. The external host mode uses twelve (12) hardware commands, which are decoded from the control signal pins, to facilitate the internal flash memory erase, program and verify processes. The external host mode is enabled on the falling edge of PSEN#. The external host mode commands are enabled on the falling edge of ALE/PROG#. The list in Table 4-1 outlines all the commands and the respective control signal assignment.
4.1 External Host Programming Mode
External Host Programming mode allows the user to program the Flash memory directly without using the CPU. External host mode is entered by forcing PSEN# from a logic high to a logic low while RST input is being held continuously high. The device will stay in external host mode as long as RST = "1" and PSEN# = "0". A Read-ID operation is necessary to "arm" the device, no other external host mode command can be enabled until a Read-ID is performed. In external host mode, the internal Flash memory blocks are accessed through the reassigned I/O port pins (see Figure 4-1 for details) by an external host, such as an MCU programmer, PCB tester or a PC controlled development board. When the chip is in the external host mode, Port 0 pins are assigned to be the parallel data input and output pins. Port 1 pins are assigned to be the non-multiplexed low order address bus signals for the internal flash memory (A7-A0). The first six bits of Port 2 pins (P2[5:0]) are assigned to be TABLE
Operation Read-ID Chip-Erase Block-Erase Sector-Erase Byte-Program Burst-Program Byte-Verify (Read) Prog-SB1 Prog-SB2 Prog-SB3 Prog-RB0 Prog-RB1
4-1: EXTERNAL HOST MODE COMMANDS
RST VIH1 VIH1 VIH1 VIH1 VIH1 VIH1 VIH1 VIH1 VIH1 VIH1 VIH1 VIH1 PSEN# VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL ALE/ PROG# VIH 1 VIH EA# VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH P3[7] VIL VIL VIH VIH VIH VIL VIH VIH VIL VIL VIH VIH P3[6] VIL VIL VIH VIL VIH VIH VIH VIH VIL VIH VIL VIL P2[7] VIL VIL VIL VIH VIH VIH VIL VIH VIH VIL VIL VIL P2[6] VIL VIH VIH VIH VIL VIL VIL VIH VIH VIH VIL VIH P0[7:0] DO X X X DI DI DO X X X X X P1[7:0] AL X X AL AL AL AL X X X X X P3[5:4] P2[5:0] AH X A[15:12] AH AH AH AH X X X X X
T4-1.5 344
1. Symbol signifies a negative pulse and the command is asserted during the low state of ALE/PROG# input. All other combinations of the above input pins are invalid and may result in unexpected behaviors. Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Locig High Level (RST); X = Don't care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:12] = 0xxxb for Block 0 (SST89C58), A[15:12] = 00xxb for Block 0 (SST89C54), and A[15:12] = "1111b" for Block 1.
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Data Sheet
VSS VDD RST XTAL1 Port 0 XTAL2
0 6 7 0 0 1 2 Busy/Ready A14 A15 3 4 5 6 7 1 2
Input/ Output Data Bus
Port 2 Port 3
3 4 5 6 7 0
Address Bus A13-A8
Address Bus A15-A14
Flash Control Signals
Flash Control Signals Address Bus A7-A0
Port 1
6 7
EA#
ALE / PSEN# PROG#
344 ILL F01.2
FIGURE
4-1: I/O PIN ASSIGNMENTS
FOR
EXTERNAL HOST MODE 4.1.2 Arming Command An arming command sequence must take place before any external host mode sequence command is recognized by the SST89C54/58. This prevents accidental triggering of external host mode commands due to noise or programmer error. The arming command is as follows: 1. PSEN# goes low while RST is high. This will set the device in external host mode, re-configuring the pins. 2. A Read-ID command is issued and held for 1 ms.
Data BFH E4H E2H
T4-2.2 344
4.1.1 Product Identification The Read-ID command accesses the signature bytes that identify the device as an SST89C54/58 and the manufacturer as SST (See Table 4-2). External programmers primarily use these signature bytes in the selection of programming algorithms. The Read-ID command is selected by the byte code of 00H on P2[7:6] and P3[7:6]. See Figure 12-12 for timing waveforms. TABLE 4-2: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST89C54 SST89C58 31H 31H 30H
After the above sequence, all other external host mode commands are enabled. Before the Read-ID command is received, all other External Host commands received are ignored.
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Data Sheet 4.1.3 External Host Mode Commands The twelve SST89C54/58 external host mode commands are Read-ID, Chip-Erase, Block-Erase Sector-Erase, ByteProgram, Burst-Program, Byte-Verify, Prog-SB1, ProgSB2, Prog-SB3, Prog-RB0 and Prog-RB1. See Table 4-1 for all signal logic assignments and Table 12-11 for the timing parameter for the external host mode commands. The critical timing for all Erase and Program commands is selfgenerated by the on-chip flash memory controller. The high-to-low transition of the PROG# signal initiates the Erase and Program commands, which are synchronized internally. The Read commands are asynchronous reads, independent of the PROG# signal level. The following three commands are used for erasing all or part of the memory array. Memory locations that are to be programmed must be in the erased state (0FFH) prior to programming. The Chip-Erase command erases all bytes in both memory blocks. This command ignores the Security Lock status and will erase the Security bits and the RE-MAP bits. See Figure 12-13 for timing waveforms. The Block-Erase command erases all bytes in one of the memory blocks (16/32KB or 4KB). This command will not be enabled if the security lock is enabled on the selected memory block. The selection of the memory block to be erased is determined by A[15:12]. If A15 is a "0", then the primary flash memory Block 0 (16/32KB), is selected. If A[15:12] = "1111b", then the secondary flash memory Block 1 (4KB) is selected. See Figure 12-14 for the timing waveforms. The Sector-Erase command erases all of the bytes in a sector. The sector size for the primary flash memory (Addresses 0000H-3FFFH/7FFFH) is 128 Bytes. The sector size for the secondary flash memory (Addresses F000H-FFFFH) is 64 bytes. This command will not be executed if the Security lock is enabled on the selected memory block. The selection of the memory sector to be erased is determined by A[15:6] for Block 0 A[15:5] for Block 1. See Figure 12-15 for timing waveforms. The Byte-Program and Burst-Program commands are used for programming new data into the memory array. Selection of which Program command to use will be dependent upon the desired programming field size. Programming will not take place if any security locks are enabled on the selected memory block. The Byte-Program command programs data into a single byte. See Figure 12-16 for timing waveforms. The Burst-Program command programs data to an entire row, sequentially byte-by-byte. See Figure 12-17 for timing waveforms. The Byte-Verify command allows the user to verify that the SST89C54/58 correctly performed an Erase or Program command. This command will be disabled if any security locks are enabled on the selected memory block. See Figure 12-18 for timing waveforms. The Prog-SB1, Prog-SB2, Prog-SB3 commands program the security bits. The functions of these bits are described in a Security Lock section and also in Table 8-1. Once programmed, these bits can only be erased through a ChipErase command. The Prog-RB1, and Prog-RB0 commands program the RE-MAP[1:0] bits. The functions of these bits are described in the Memory Re-mapping section and also in Table 3-1. Once programmed, these bits can only be erased through Chip-Erase command.
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Data Sheet 4.1.4 External Host Mode Clock Source In external host mode, an internal oscillator will provide clocking for the SST89C54/58. The on-chip oscillator will be turned on as the SST89C54/58 enters external host mode; i.e. when PSEN# goes low while RST is high. The oscillator provides both clocking for the flash control unit as well as timing references for Program and Erase operations. During external host mode, the CPU core is held in reset. Upon exit from external host mode, the internal oscillator is turned off. The same oscillator also provides the time base for the watchdog timer and timing references for IAP mode Program and Erase operations. See more detailed description in later sections. 4.1.5 Flash Operation Status Detection Via External Host Handshake The SST89C54/58 provide two methods for an external host to detect the completion of a flash memory operation to optimize the Program or Erase time. The end of a flash memory operation cycle can be detected by: 1) monitoring the READY/BUSY# bit at P3[3]; 2) monitoring the Data# Polling bit at P0[7] and P0[3]. 4.1.5.1 Ready/Busy# (P3[3]) The progress of the flash memory programming can be monitored by the READY/BUSY# output signal. P3[3] is driven low, some time after ALE/PROG# goes low during a flash memory operation to indicate the Busy# status of the flash control unit (FCU). P3[3] is driven high when the Flash programming operation is completed to indicate the Ready status. During a Burst-Program operation, P3[3] is driven high (Ready) in between each byte programmed among the burst to indicate the ready status to receive the next byte. When the external host detects the Ready status after a byte among the burst is programmed, it should then put the data/address (within the same row) of the next byte on the bus and drive ALE/PROG# low (pulse), before the time-out limit expires. See Table 12-11 for details. Burst-Program command presented after time-out will wait until the next cycle. Therefore, it will have longer programming time. 4.1.5.2 Data# Polling (P0[7] and P0[3]) During a Program operation, any attempts to read (ByteVerify), while the device is busy, will receive the complement of the data for the last byte loaded (logic low, i.e. "0" for an erase) on P0[3] and P0[7] with the rest of the bits "0". During a Program operation, the Byte-Verify command will read the data from the last byte loaded, not the data at the address specified. During a Burst-Program operation, the true data will be read from P0[7], when the device completes each byte programmed among the burst to indicate the Ready status to receive the next byte. When the external host detects the Ready status after a byte among the burst is programmed, it should then put the data/address (in the same row) of the next byte on the bus and drive ALE/PROG# low immediately, before the time-out limit expires (See Table 12-11 for details.). The true data will be read from P0[3], when the Burst-Program command is terminated and the device is ready for the next operation. After security lock-bits are set: * * If read on universal programmer, e.g. external host mode, the programmer will read 00H instead of 0FFH. If read by MOVC instruction, the programmer will return 0FFH regardless of true data if MOVC is executed in a block with lower level lock. If read by the IAP Byte-Verify command, then SFDT won't update its data, i.e. SFDT will keep its OLD data unchanged, so the user's application code will get random data based on the old SFDT value. This IAP Byte-Verify command is executed in a block with lower level lock.
*
The termination of the Burst-Program can be accomplished by: 1) Change to a new row address (Note: the Address range is different for the 4Kx8 flash Block 1 and for the 16/32K x 8 flash Block 0.); 2) Change to a new command that requires a high to low transition of the ALE/ PROG# (for example, any Erase or Program command, 3) Wait for time out limit to expire (20 s) before programming the next byte.
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Data Sheet 4.1.6 Instructions to Perform External Host Mode Commands To program data into the memory array, apply power supply voltage (VDD) to VDD and RST pins, and perform the following steps: 1. Maintain RST high and toggle PSEN# from logic high to low, in sequence per the appropriate timing diagram. 2. Raise EA# High (either VIH or VH). 3. Issue Read-ID command to enable the external host mode. 4. Verify that the memory blocks or sectors for programming is in the erased state, FFH. If they are not erased, then erase them using the appropriate Erase command. 5. Select the memory location using the address lines (P1[7:0], P2[5:0], P3[5:4]). 6. Present the data in on P0[7:0]. 7. Pulse ALE/PROG#, observing minimum pulse width. 8. Wait for low to high transition on READY/BUSY# (P3[3]). 9. Repeat steps 5 - 8 until programming is finished. 10. Verify the flash memory contents.
4.2 In-Application Programming Mode
The SST89C54/58 offers 20/36 KByte of in-application programmable flash memory. During in-application programming, the CPU of the microcontroller enters IAP mode. The two blocks of flash memory allows the CPU to concurrently execute user code from one block, while the other is being reprogrammed. The CPU may also fetch code from an external memory while all internal flash is being reprogrammed. The mailbox registers (SFST, SFCM, SFAL, SFAH, SFDT and SFCF) located in the Special Function Register (SFR), control and monitor the device's erase and program process. Table 4-3 outlines the commands and their associated settings of the mailbox registers. 4.2.1 In-Application Programming Mode Clock Source During IAP mode, both the CPU core and the flash controller unit (FCU) are driven off the external clock. However, an internal oscillator will provide timing references for Program and Erase operations. The duration of Program and Erase operations will be identical between external host mode and In-Application mode. The internal oscillator is only turned on when required, and is turned off as soon as the Flash operation is complete. 4.2.2 IAP Enable Bit The IAP enable bit, SFCF[6], initializes in-application programming mode. Until this bit is set, all flash programming IAP commands will be ignored.
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Data Sheet 4.2.3 In-Application Programming Mode Commands All of the following commands can only be initiated in the IAP mode. In all situations, writing the control byte to the (SFCM) register will initiate all of the operations. All commands (except Chip-Erase) will not be enabled if the security features are enabled on the selected memory block. The two Program commands are for programming new data into the memory array. The portion of the memory array to be programmed should be in the erased state, FFH. If the memory is not erased, then erase it with an appropriate Erase command. Do not write (Program or Erase) to a block that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data. The Chip-Erase command erases all bytes in both memory blocks (16/32KB and 4KB). This command ignores the Security Lock status and will erase the security lock bits and RE-MAP bits. The Chip-Erase command sequence is as follows:
IAP Enable ORL SFCF, #40H Erase 32 KBlock MOV SFAH, #00H Erase 4 KBlock MOV SFAH, #F0H
OR
Set-Up MOV SFDT, #55H
Polling scheme MOV SFCM, #0DH
Interrupt scheme MOV SFCM, #8DH
SFST[2] indicates operation completion
INT1 interrupt indicates completion
344 ILL F40.8
IAP Enable ORL SFCF, #40H Set-Up MOV SFDT, #55H
The Sector-Erase command erases all of the bytes in a sector. The sector size for the primary flash memory Block 0 is 128 Bytes. The sector size for the secondary flash memory Block 1 is 64 Bytes. The selection of the sector to be erased is determined by the contents of SFAH, SFAL. Please refer to Figure 3-1 for an illustration of memory sector organization. The Sector-Erase command sequence is as follows:
Polling scheme MOV SFCM, #01H
Interrupt scheme MOV SFCM, #81H
IAP Enable ORL SFCF, #40H Load sector address MOV SFAH, #sector_addressH MOV SFAL, #sector_addressL
SFST[2] indicates operation completion
INT1 interrupt indicates completion
344 ILL F39.4
The Block-Erase command erases all bytes in one of the two memory blocks (16/32KB or 4KB). The selection of the memory block to be erased is determined by the (SFAH[7]) of the SuperFlash Address Register. The primary flash memory Block 0 is selected (16/32KB) as follows: for SST89C58, SFAH[7] = 0 selects Block 0; for SST89C54, SFAH[7:6] = 00 selects Block 0. For both, SFAH[7:4] = 1111b selects the secondary flash memory Block 1 (4KB). The Block-Erase command sequence is as follows:
Polling scheme MOV SFCM, #0BH
Interrupt scheme MOV SFCM, #8BH
SFST[2] indicates operation completion
INT1 interrupt indicates completion
344 ILL F41.6
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Data Sheet The Byte-Program command programs data into a single byte location. The Byte-Program command sequence is as follows: The Burst-Program command programs data into half of a sector (row) which has the same row address, sequentially byte-by-byte. Refer to the Memory Organization section in Figure 3-1 for details. The MOVC instruction and all IAP commands except Burst-Program are invalid during the Burst-Program cycle. The Burst-Program command sequence is as follows:
IAP Enable ORL SFCF, #40H
Load byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL
IAP Enable ORL SFCF, #40H
Move data to SFDT MOV SFDT, #data
Load byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL
Move data to SFDT MOV SFDT, #data
Polling scheme MOV SFCM, #0EH
Interrupt scheme MOV SFCM, #8EH
Polling scheme MOV SFCM, #06H
Interrupt scheme MOV SFCM, #86H
SFST[2] indicates operation completion
INT1 interrupt indicates completion
344 ILL F42.6
Next same row address
SFST[3] indicates byte completion
INT1 interrupt indicates completion
Y
Program another byte N
SFST[2] indicates Burst-Program completion
344 ILL F43.8
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Data Sheet The Byte-Verify command allows the user to verify that the SST89C54/58 has correctly performed an Erase or Program command. Byte-Verify command returns the data byte in SFDT. The user is required to check that the previous Flash operation has fully completed before issuing a Byte-Verify. Byte-Verify command execution time is short enough that there is no need to poll for command completion and no interrupt is generated. The Byte-Verify command sequence is as follows: Prog-RB1, Prog-RB0 commands are used to program the RE-MAP[1:0] bits (see Table 3-1). These commands only change the RE-MAP[1:0] bits and have no effect on MapEn[1:0] until after a reset cycle. Therefore, the effect of these commands is not immediate. Re-Map bits previously in un-programmed state can be programmed by these commands. The Prog-RB1, ProgRB0 sequences are as follows:
IAP Enable ORL SFCF, #40H Load byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL
IAP Enable ORL SFCF, #40H
Set-Up MOV SFAH, #80H MOV SFDT, #55H
MOV SFCM, #0CH
Program Re-Map [0] MOV SFCM, #08H or MOV SFCM, #88H
Program Re-Map [1] MOV SFCM, #09H or MOV SFCM, #89H
SFDT register contains data
344 ILL F44.5
Polling SFST[2] indicates completion
OR
INT1# Interrupt indicates completion
344 ILL F46.6
Prog-SB3, Prog-SB2, Prog-SB1 commands are used to program the Security bits (see Table 8-1). Upon completion of any of those commands, the security options will be updated immediately. Security bits previously in un-programmed state can be programmed by these commands. The Prog-SB3, ProgSB2, Prog-SB1 sequences are as follows:
Prog-SB3, Prog-SB2, Prog-SB1, Prog-RB1, and Prog-RB0 commands must reside only in Block 0 (32 KByte block) or external code memory. Any such instructions issued from Block 1 may cause unpredictable program behavior. 4.2.4 Polling
IAP Enable ORL SFCF, #40H
Set-Up MOV SFAH, #80H MOV SFDT, #55H
A command that uses the polling method to detect flash operation completion should poll on the Flash_busy bit (SFST[2]). When Flash_busy de-asserts (logic 0), the device is ready for the next operation. The BUSY bit (SFST[3]) is provided for Burst-Program. In between bytes within a burst sequence, the Busy bit will become logic 0 to indicate that the next Burst-Program byte should be presented. Completion of the full burst cycle is indicated also by Flash_busy bit (SFST[2]). MOVC instruction may also be used for verification of the Programming and Erase operation of the flash memory. MOVC instruction will fail if it is directed at a flash block that is still busy.
Program SB1 MOV SFCM, #0FH OR or MOV SFCM, #8FH
Program SB2 MOV SFCM, #03H or MOV SFCM, #83H
OR
Program SB3 MOV SFCM, #05H or MOV SFCM, #85H
Polling SFST[2] indicates completion
OR
INT1# Interrupt indicates completion
344 ILL F45.7
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Data Sheet 4.2.5 Interrupt Termination If interrupt termination is selected, (SFCM[7] is set), then an interrupt (INT1) will be generated to indicate flash operation completion. Under this condition, the INT1 becomes an internal interrupt source. The INT1# pin can now be used as a general purpose port pin and it cannot be a source of External Interrupt 1. For an interrupt to occur, EX1 and EA bits of IE register must be set. The IT1 bit of TCON register must also be set for edge trigger detection. Important: The user cannot program Security/Re-Map bits while code is running in Block 1. The user can only program security SBx/Re-Map bits when code is running in external code memory or when code is running in Block 0. The solution is to use MOV SFAH, #80H; before issuing any IAP commands to program security bits or Re-Map bits. TABLE
Operation Chip-Erase Block-Erase Sector-Erase Byte-Program Burst-Program Byte-Verify (Read)
4-3: IN-APPLICATION PROGRAMMING MODE COMMANDS
SFAH [7:0] X AH2 AH AH AH AH 80H 80H 80H 80H 80H SFAL [7:0] X X AL AL AL AL X X X X X SFDT [7:0] 55H 55H X DI DI DO 55H 55H 55H 55H 55H SFCM [6:0]1 01H 0DH 0BH 0EH 06H 0CH 05H 03H 0FH 09H 08H
T4-3.4 344
Prog-SB3 Prog-SB2 Prog-SB1 Prog-RB1 Prog-RB0
1. Interrupt/Polling enable for flash operation completion SFCM[7] = 1: Interrupt enable for flash operation completion 0: polling enable for flash operation completion 2. SFAH[7] = 0 selects Block 0 for SST89C58; SFAH[7:6] = 00 selects Block 0 for SST89C54; SFAH[7:4] = FH selects Block 1 Note: X = Don't Care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output All other values are in hex. SFCF[6] = 1 enables IAP command. SFCF[6] = 0 disables IAP command.
5.0 TIMERS/COUNTERS
The SST89C54/58 have three 16-bit registers that can be used as either timers or event counters. The three Timers/Counters are the Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated with a pair of 8-bit registers in the SFRS. The pair consists of a most significant (high) byte and least significant (low) byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2.
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Data Sheet
6.0 SERIAL I/O
The SST89C54/58 serial I/O port is a full-duplex UART (Universal Asynchronous Receiver/Transmitter) that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respectively. The serial I/O port performs the function of an UART. The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function register. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the contents of the receive register. The serial I/O port has four modes of operation which are selected by the Serial Port mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated in Mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) special function register is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in other modes by the incoming start bit if the REN bit of the SCON register is set.
7.0 WATCHDOG TIMER
The SST89C54/58 offer a hardware programmable Watchdog Timer (WDT) for fail safe operation against software hangup and automatic reset recovery. To protect the system against software hangup, the software has to refresh the WDT within a user defined time period. If the software fails to do this periodic refresh, an internal hardware reset will be initiated if enabled (WDRE=1). The software can be designed such that the WDT times out if the program does not work properly. It also times out if a software error is based on hardware related problems. The WDT in the SST89C54/58 share the same time base with the flash controller unit. When the flash controller unit is operating, the time base will be re-started by the hardware periodically, therefore delaying the time-out period of the watchdog timer. The upper 8-bits of the time base register are used as the reload register of the WDT. The internal oscillator that drives the WDT operates within a frequency range as shown in Table 12-1. Minimum clock cycle for the WDT is 7.7ms, typical 10ms. Figure 7-1 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer operation. Note: * WDTD won't be effective until bit WDT is set. * A WDTD register can not be set to 0FFH. * WDT timeout period = (255-WDTD) x 7.7ms (min.)
CLK
Counter
7.7 ms min. WDT Upper Byte
WDT Reset
Internal Reset
Ext. RST
WDTC
WDTD
344 ILL F10.2
FIGURE
7-1: BLOCK DIAGRAM
OF
PROGRAMMABLE WATCHDOG TIMER
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Data Sheet
8.0 SECURITY LOCK
The Security feature protects against software piracy and prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory locations. There are two different types of security locks in the SST89C54/58 security lock system, hard lock and SoftLock. (See Figure 8-1 and Table 8-1.) from a hard locked block can be operated on a SoftLocked block: Block-Erase, Sector-Erase, Byte-Program, BurstProgram and Byte-Verify. In external host mode, SoftLock behaves the same as a hard lock.
8.3 Security Lock Status
The three bits that indicate the SST89C54/58 security lock status, SB1, SB2 and SB3, are located in SFST[7:5]. As shown in Figure 8-1 and Table 8-1, the three security lock bits control the lock status of the primary and secondary blocks of memory. There are four distinct levels of security lock status. In the first level, none of the security lock bits are programmed and both blocks are unlocked. In the second level, although, both blocks are now locked and cannot be written, they are available for Read operation via ByteVerify. In the third level, three different options are available: Block 1 hard lock / Block 0 SoftLock, SoftLock on both blocks, and hard lock on both blocks. Locking both blocks is the same as Level 2 except Read operation isn't available. The fourth level of security is the most secure level. It doesn't allow read/write of internal memory or boot from external memory. Please note that for unused combinations of the security lock bit the chip will default to Level 4 status. For details on how to program the security lock bits, refer to the External Host Programming Mode (Section 4.1) and inapplication programming mode (Section 4.2).
8.1 Hard Lock
When the hard lock is activated, the MOVC instructions executed from unlocked or SoftLocked program address space, are disabled from reading code bytes in hard locked memory blocks (See Table 8-2). The hard lock can either lock both flash memory blocks or just lock the upper flash memory block (Block 1). All External Host and IAP commands except for Chip-Erase are ignored by the hard locked memory blocks.
8.2 SoftLock
SoftLock allows flash contents to be altered under a secure environment. This lock option allows the user to update program code in the SoftLocked memory block through inapplication programming mode under a predetermined secure environment. For example, if the Block 1 (4KB) memory is hard locked, and the Block 0 (16KB/32KB) memory is SoftLocked, code residing in Block 1 can program Block 0. The following IAP mode commands issued through the command mailbox register, SFCM, executed
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Data Sheet
UUU/NN
Level 1 Level 2
PUU/LL
UPU/SS
UUP/LS
Level 3
PPU/LL = PUP/LL
PPP/LL
Level 4
344 ILL F38.1
Note: P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1) N = Not Locked, L = Hard Locked, S = SoftLocked
FIGURE TABLE
Level 1 2
8-1: SECURITY LOCK LEVELS
8-1: SECURITY LOCK OPTIONS
Security Lock Bits1,2 SFST[7:5] 000 100 SB1 U P SB2 U U SB3 U U Security Status of: Block 1 Unlock Hard Lock Block 0 Unlock Security Type No Security Features are Enabled.
Hard Lock MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA# is sampled and latched on Reset, and further programming of the flash is disabled. Hard Lock Level 2 plus Verify disabled, both blocks locked. SoftLock SoftLock Level 2 plus Verify disabled, code in Block 1 can program Block 0 and vice versa. Level 2 plus Verify disabled, code in Block 1 can program Block 0.
3
110 101 010 001
P P U U P
P U P U P
U P U P P
Hard Lock SoftLock Hard Lock Hard Lock
4
111
Hard Lock Same as Level 3, Hard Lock/Hard Lock but MCU will start code execution from the internal memory regardless of EA#.
T8-1.7 344
1. SFST[7:5] = Security Lock Decoding Bits (SB1, SB2, SB3) 2. P = Programmed (Cell logic state = 0); U = Unprogrammed (Cell logic state = 1) All unused combinations default to level 4, "PPP"
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Data Sheet TABLE
Level
8-2: SECURITY LOCK ACCESS TABLE
SFST[7:5]
111b/011b4 (Hard Lock on both blocks)
Source Address1
Block 0/1 External Block 0/1
Target Address2
Block 0/1 External Block 0/1 External Block 0/1 External Block 0/1 External Block 0 Block 1 External Block 0
Byte-Verify Allowed External Host3
N N/A N N/A N N/A N N/A N N N/A N N N/A N N/A N N N/A N N N/A N N/A Y Y N/A Y Y N/A Y N/A Y Y N/A Y Y N/A Y N/A
IAP
N N/A N N/A N N/A N N/A N N N Y N N/A N N/A N Y N/A Y N N/A N N/A N N N/A N N N/A N N/A N Y N/A Y N N/A Y N/A
MOVC Allowed on C58/54
Y Y N Y Y Y N Y Y N5 Y Y Y Y N Y Y Y Y Y Y Y N Y Y Y Y Y Y Y N Y Y Y Y Y Y Y Y Y
T8-2.1 344
4
101b/110b (Hard Lock on both blocks) External
Block 0 001b (Block 0 = SoftLock, Block 1 = Hard Lock) 3 External
Block 1
Block 1 External Block 0/1 External Block 0 Block 1 External Block 0
Block 0
010b (SoftLock on both blocks)
Block 1
Block 1 External Block 0/1 External Block 0 Block 1 External Block 0
External
Block 0
2
100b (Hard Lock on both blocks)
Block 1
Block 1 External Block 0/1 External Block 0 Block 1 External Block 0
External
Block 0
1
000b (Unlock)
Block 1
Block 1 External Block 0/1 External
External 1. 2. 3. 4. 5.
Location of MOVC or IAP instruction. Target Address is the location of the instruction being read. External Host Byte-Verify access does not depend on a source address. 011b is an unused combination and defaults to security level 4 MOVC is normally not allowed when accessing data in Block 1 at addresses F000H-FFFFH. MOVC is allowed when Block 1 is re-mapped and target address is within 0000H-03FFH/07FFH/0FFFH (1K/2K/4K re-map).
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Data Sheet
9.0 RESET
A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the SST89C54/58 is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ALE and PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level in order to perform correct reset. This level must not be affected by external element. A system reset will not affect the 256 Bytes of on-chip RAM while the SST89C54/ 58 is running, however, the contents of the on-chip RAM during power up are indeterminate. All Special Function Registers (SFR) return to their reset values, which are outlined in Tables 3-3 to 3-7. When power is applied to the SST89C54/58, the RST pin must be high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid Power-On Reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10F capacitor and to VSS through an 8.2 Kohm resistor as shown in Figure 10-1. Note that if an RC circuit is being used, provisions should be made to ensure the VDD rise time does not exceed 10 ms. The oscillator startup time depends on the crystal frequency.
Crystal 10MHz 1MHz Typical Start-up Time 1ms 10ms
9.1 Power-On Reset
At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins high. Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash.
For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location, which may cause corruption in the flash memory.
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Data Sheet
10.0 POWER-SAVING MODES
The SST89C54/58 provides power saving modes of operation for applications where power consumption is critical. The two power saving modes are: Power Down and Standby (Stop Clock). which invoked the Power Down mode. The hardware reset redefines all the SFRs but does not change the on-chip RAM.
10.2 Standby Mode (Stop Clock) 10.1 Power Down Mode
The Power Down mode is entered by setting the PD bit in the PCON register. In Power Down mode, the clock is stopped and external interrupts are active for level sensitive interrupt only. The SST89C54/58 exits Power Down mode through either an enabled external level sensitive interrupt INTx or a hardware reset. The interrupt clears the PD bit, the oscillator restarts and stablizes, then the program resumes execution beginning at the instruction immediately following the one Standby mode is similar to Power Down mode, except that Power Down mode is initiated by a software command and Standby mode is initiated by external hardware gating off the external clock to the SST89C54/58. The on-chip RAM and SFR data are maintained in the Standby mode. The device resumes operation at the next instruction when the clock is reapplied to the part. Table 10-1 outlines the two power-saving modes, including entry and exit procedures and MCU functionality.
VDD + 10F RST 8.2K SST89C54/58 C2 XTAL2
12MHz
VDD
XTAL1 C1
344 ILL F31.1
FIGURE 10-1: POWER-ON RESET CIRCUIT
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Data Sheet TABLE 10-1: SST89C54/58 POWER SAVING MODES
Mode Power Down Mode Initiated by Software (Set PD bit in PCON) MOV PCON, #02H Current Drain State of MCU Exited by Enabled external level sensitive interrupt INTx or hardware reset. Start of interrupt clears PD bit and exits Power Down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Power Down mode. A user could consider placing two or three NOP instructions after the instruction that invokes Power Down mode to eliminate any problems, or by hardware reset. Gate ON external clock. Program execution resumes at the instruction following the one during which the clock was gated off. Typically 15-20 A. Min- CLK is stopped. Onchip SRAM and SFR imum VDD for Power Down mode is 2.7V. data will be maintained. ALE and PSEN# signals at a LOW level during Power Down. External Interrupts are only active for level sensitive interrupts, if enabled.
Standby (Stop Clock) Mode
External hardware Typically 15-20 A. Mingates turn off the exter- imum VDD for Standby mode is 2.7V. nal clock input to the MCU. This gating should be synchronized with an input clock transition (low-tohigh or high-to-low).
CLK is frozen. On-chip RAM and SFR data is maintained. ALE and PSEN# are maintained at the levels prior to the clock being frozen.
T10-1.5 344
11.0 CLOCK INPUT OPTIONS
Shown in Figure 11-1 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven. At start-up, the external crystal oscillator may encounter a higher capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15pF once the external signal meets the VIL and VIH specifications.
11.1 Recommended Capacitor Values for Crystal Oscillator
Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. C1 and C2 capacitors should be adjusted appropriately for each design. Table 11-1 below, shows the typical values for C1 and C2 by crystal type. TABLE 11-1: RECOMMENDED VALUES C2 BY CRYSTAL TYPE
Crystal Quartz Ceramic
FOR
C1
AND
C1 = C2 20-30pF 40-50pF
T11-1.1 344
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Data Sheet
XTAL2 C2 C1 XTAL1 Vss EXTERNAL OSCILLATOR SIGNAL NC XTAL2 XTAL1 Vss
Using the On-Chip Oscillator
FIGURE 11-1: OSCILLATOR CHARACTERISTICS
External Clock Drive
344 ILL F12.2
12.0 ELECTRICAL SPECIFICATION
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to + 150C Voltage on EA# Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V Transient Voltage (<20ns) on Any Other Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +6.5V Maximum IOL per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum IOL per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption.) Note: This specification contains preliminary information on new products in production. The specifications are subject to change without notice.
TABLE 12-1: OPERATING RANGE
Symbol Ta Description Ambient Temperature Under Bias Standard Industrial VDD fOSC Supply Voltage Oscillator Frequency For in-application programming 0 -40 2.7 0 0.25 +70 +85 5.5 33 33 Min. Max Unit
C C
V MHz MHz
T12-1.0 344
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Data Sheet TABLE 12-2: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T12-2.1 344
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12-3: AC CONDITIONS
OF
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 12-6 and 12-8
T12-3.0 344
TABLE 12-4: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
T12-4.0 344
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 12-5: PIN IMPEDANCE
Parameter CI/O1 CIN
1
(VDD=3.3V, Ta=25 C, f=1 MHz, other pins open)
Description I/O Pin Capacitance2 Input Capacitance Pin Inductance
Test Condition VI/O = 0V VIN = 0V
Maximum 15 pF 12 pF 20 nH
T12-5.1 344
LPIN
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Pin capacitance is characterized but not tested. EA# pin is 25 pF max.
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Data Sheet
12.1 DC Electrical Characteristics
TABLE 12-6: DC ELECTRICAL CHARACTERISTICS Ta = -40C TO +85C, 33MHZ DEVICES; VDD = 4.5-5.5V; VSS = 0V
Limits Symbol VIL VIH VIH1 VOL VOL Parameter Input Low Voltage Input High Voltage (Ports 0,1,2,3) Input High Voltage (XTAL1, RST) Output Low Voltage (Ports 1.5, 1.6, 1.7) Output Low Voltage (Ports 1, 2, 3)1 Test Conditions 4.5 < VDD < 5.5 4.5 < VDD < 5.5 4.5 < VDD < 5.5 VDD = 4.5V IOL = 16 mA VDD = 4.5V IOL = 100 A2 IOL = 1.6 VOL1 Output Low Voltage (Port 0, ALE, PSEN#)1,3 mA2 IOL = 3.5 mA2 VDD = 4.5V IOL = 200 A2 IOL = 3.2 VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 mA2 VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 -1 -75 -650 10 40 225 VDD = 4.5V IOH = -10 A IOH = -30 A IOH = -60 A VOH1 Output High Voltage (Port 0 in External Bus Mode)4 VDD = 4.5V IOH = -200 A IOH = -3.2 mA IIL ITL ILI RRST IDD Logical 0 Input Current (Ports 1, 2, 3) Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 Input Leakage Current (Port 0) RST Pulldown Resistor Power Supply Current6 In-Application Programming mode @ 12 MHz @ 33 MHz Active Mode @ 12 MHz @ 33 MHz Standby (Stop Clock) Mode Power Down Mode Ta = 0C to +70C Ta = -40C to +85C Minimum VDD = 2.7V Ta = 0C to +70C Ta = -40C to +85C 40 50 A A
T12-6.8 344
Min -0.5 0.2VDD + 0.9 0.7VDD
Max 0.2 VDD - 0.1 VDD + 0.5 VDD + 0.5 1.0 0.3 0.45 1.0 0.3 0.45
Units V V V V V V V V V V V V V V A A A k
VIN = 0.4V VIN = 2V 0.45 < VIN < VDD-0.3
70 88 22 45 100 125
mA mA mA mA A A
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Data Sheet TABLE 12-7: DC ELECTRICAL CHARACTERISTICS Ta = -40C TO +85C, 12MHZ DEVICES; VDD = 3.0-3.6V; VSS = 0V
Limits Symbol VIL VIH VIH1 VOL VOL Parameter Input Low Voltage Input High Voltage (ports 0, 1, 2, 3) Input High Voltage (XTAL1, RST) Output Low Voltage (Ports 1.5, 1.6, 1.7) Output Low Voltage (Ports 1, 2, 3)1 Test Conditions 2.7 < VDD < 3.3 2.7 < VDD < 3.3 2.7 < VDD < 3.3 VDD = 2.7V IOL = 16 mA VDD = 2.7V IOL = 100 A2 IOL = 1.6 mA2 IOL = 3.5 mA2 VOL1 Output Low Voltage (Port 0, ALE, PSEN#)1,3 VDD = 2.7V IOL = 200 A2 IOL = 3.2 mA2 VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 VDD = 2.7V IOH = -10 A IOH = -30 A IOH = -60 A VOH1 Output High Voltage (Port 0 in External Bus Mode)4 VDD = 2.7V IOH = -200 A IOH = -3.2 mA IIL ITL ILI RRST IDD Logical 0 Input Current (Ports 1, 2, 3) Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 Input Leakage Current (Port 0) RST Pulldown Resistor Power Supply Current6 In-Application Programming mode Active Mode Standby (Stop Clock) Mode Power Down Mode Ta = 0C to +70C Ta = -40C to +85C Minimum VDD = 2.7V Ta = 0C to +70C Ta = -40C to +85C 40 50 A A
T12-7.6 344
Min -0.5 0.2VDD + 0.9 0.7VDD
Max 0.7 VDD + 0.5 VDD + 0.5 1.0 0.3 0.45 1.0 0.3 0.45
Units V V V V V V V V V V V V V V
VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 -1 -75 -650 10 40 225 70 22 70 88
VIN = 0.4V VIN = 2V 0.45 < VIN < VDD-0.3
A A A k mA mA A A
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: Maximum IOL total for all outputs: 71mA If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Load capacitance for Port 0, ALE & PSEN# = 100pF, load capacitance for all other outputs = 80pF. 4. Capacitive loading on Ports 0 & 2 may cause the VOH, ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the address bits are stabilizing.
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Data Sheet
5. Pins for Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 6. See Figures 12-9, 12-10 and 12-11 and for test conditions. Minimum VDD for Power Down is 2.7V.
12.2 AC Electrical Characteristics
AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 12-8: AC ELECTRICAL CHARACTERISTICS (1 OF 2) Ta = -40C TO +85C, VDD = 3.0-3.6V @12MHZ,4.5-5. 5V @ 33MHZ, VSS = 0
Oscillator 12MHz Symbol 1/TCLCL TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX Parameter Min 127 43 5 53 5 234 55 53 5 205 145 35 0 59 5 75 312 70 10 400 400 252 60 0 106 35 517 150 585 180 200 203 45 33 0 300 40 140 3TCLCL - 50 4TCLCL - 130 (3V) 4TCLCL - 75 (5V) TCLCL - 50 (3V) TCLCL - 30 (5V) 0 0 2TCLCL - 60 (3V) 2TCLCL - 25 (5V) 8TCLCL - 90 (3V) 8TCLCL - 90 (5V) 9TCLCL - 90 (3V) 9TCLCL - 90 (5V) 3TCLCL + 50 80 80 10 6TCLCL - 100 6TCLCL - 100 5TCLCL - 90 (3V) 5TCLCL - 90 (5V) 22 TCLCL - 8 5TCLCL - 80 (3V) 5TCLCL - 80 (5V) 10 0 0 TCLCL - 25 (3V) TCLCL - 25 (5V) 45 TCLCL - 30 (3V) TCLCL - 25 (5V) 3TCLCL - 45 3TCLCL - 55 (3V) 3TCLCL - 55 (5V) Max 33MHz Min 20 Max Min 0 2TCLCL - 40 TCLCL - 40 (3V) TCLCL - 25 (5V) TCLCL - 30 (3V) TCLCL - 25 (5V) 4TCLCL - 65 (3V) 4TCLCL - 65 (5V) Variable Max 33 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr In ALE Low to PSEN# Low PSEN# Pulse Width PSEN# Low to Valid Instr In Input Instr Hold After PSEN# Input Instr Float After PSEN# PSEN# to Address Valid Address to Valid Instr In PSEN# Low to Address Float RD# Pulse Width Write Pulse Width (WE#) RD# Low to Valid Data In Data Hold After RD# Data Float After RD# ALE Low to Valid Data In Address to Valid Data In ALE Low to RD# or WR# Low Address to RD# or WR# Low Data Valid to WR# Transition
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Data Sheet TABLE 12-8: AC ELECTRICAL CHARACTERISTICS (CONTINUED) (2 OF 2) Ta = -40C TO +85C, VDD = 3.0-3.6V @12MHZ,4.5-5. 5V @ 33MHZ, VSS = 0
Oscillator 12MHz Symbol TWHQX TQVWH TRLAZ TWHLH Parameter Min 33 3 433 140 0 43 123 5 55 0 TCLCL - 40 (3V) TCLCL - 25 (5V) Max 33MHz Min Max Min TCLCL - 50 (3V) TCLCL - 27 (5V) 7TCLCL - 150 (3V) 7TCLCL - 70 (5V) 0 TCLCL + 25 (3V) TCLCL + 25 (5V) Variable Max Units ns ns ns ns ns ns ns
T12-8.3 344
Data Hold After WR# Data Valid to WR# High RD# Low to Address Float RD# to WR# High to ALE High
Explanation of Symbols Each timing symbol has 5 characters. The first character is always a `T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: C: D: H: I: L: P: Address Clock Input data Logic level HIGH Instruction (program memory contents) Logic level LOW or ALE PSEN# Q: R: T: V: W: X: Z: Output data RD# signal Time Valid WR# signal No longer a valid logic level High Impedance (Float)
For example: TAVLL = Time from Address Valid to ALE Low TLLPL = Time from ALE Low to PSEN# Low
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Data Sheet
TLHLL
ALE
TAVLL TLLPL TPLAZ TLLAX TLLIV TPLIV TPXAV TPXIZ TPXIX INSTR IN A0 - A7 TPLPH
PSEN#
PORT 0
A0 - A7 TAVIV
PORT 2
A8 - A15
A8 - A15
344 ILL F13.5
FIGURE 12-1: EXTERNAL PROGRAM MEMORY READ CYCLE
TLHLL
ALE
TWHLH
PSEN#
TLLDV TRLRH TLLWL
RD#
TAVLL
TLLAX TRLAZ TRLDV
TRHDZ TRHDX
PORT 0
A0-A7 FROM RI or DPL TAVWL TAVDV
DATA IN
A0-A7 FROM PCL
INSTR IN
PORT 2
P2[0:7] or A8-A15 FROM DPH
A8-A15 FROM PCH
344 ILL F14.4
FIGURE 12-2: EXTERNAL DATA MEMORY READ CYCLE
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Data Sheet
TLHLL
ALE
TWHLH
PSEN#
TLLWL TWLWH
WR#
TAVLL
TLLAX TQVWX TQVWH
TWHQX
PORT 0
A0-A7 FROM RI or DPL TAVWL
DATA OUT
A0-A7 FROM PCL
INSTR IN
PORT 2
P2[0:7] or A8-A15 FROM DPH
A8-A15 FROM PCH
344 ILL F15.4
FIGURE 12-3: EXTERNAL DATA MEMORY WRITE CYCLE TABLE 12-9: EXTERNAL CLOCK DRIVE
Oscillator 12MHz Symbol 1/TCLCL TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 83 Max 33MHz Min 30 10.5 10.5 20 20 5 5 Max Min 0 0.35TCLCL 0.35TCLCL Variable Max 33 0.65TCLCL 0.65TCLCL Units MHz ns ns ns ns ns
T12-9.3 344
VDD -0.5
0.7 VDD 0.2 VDD -0.1 TCLCX TCHCL TCLCL TCHCX TCLCH
344 ILL F30.1
0.45 V
FIGURE 12-4: EXTERNAL CLOCK DRIVE WAVEFORM
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Data Sheet TABLE 12-10: SERIAL PORT TIMING
Oscillator 12MHz Symbol Parameter TXLXL TQVXH TXHQX TXHDX TXHDV Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid Min 1 700 50 10 0 700 0 167 Max 33MHz Min 0.36 167 Max Min 12TCLCL 10TCLCL - 133 2TCLCL - 117 2TCLCL - 50 0 10TCLCL - 133 Variable Max Units s ns ns ns ns ns
T12-10.2 344
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
TXLXL
CLOCK
TQVXH TXHQX
OUTPUT DATA WRITE TO SBUF INPUT DATA CLEAR RI
0
1
TXHDV VALID VALID
2
TXHDX VALID
3
4
5
6
7
SET TI
VALID
VALID
VALID
VALID
VALID
SET R I
344 ILL F29.0
FIGURE 12-5: SHIFT REGISTER MODE TIMING WAVEFORMS
VIHT
VHT VLT
344 ILL F28a.2
VLOAD +0.1V VLOAD Timing Reference Points
VOL -0.1V VOL +0.1V
344 ILL F28b.3
VILT
VLOAD -0.1V
AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and VILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1)
Note: VHT- VHIGH Test VLT- VLOW Test VIHT-VINPUT HIGH Test VILT- VINPUT LOW Test
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH = 20mA.
FIGURE 12-6: AC INPUT/OUTPUT TEST WAVEFORMS
FIGURE 12-7: FLOAT WAVEFORM
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Data Sheet
TO TESTER
TO DUT CL
344 ILL F48.0
FIGURE 12-8: A TEST LOAD EXAMPLE
VDD VDD VDD RST 8XC5X CLOCK SIGNAL (NC) XTAL2 XTAL1 VSS
344 ILL F26.0
VDD = 5V
VDD
IDD
VDD P0 RST 8XC5X (NC) XTAL2 XTAL1 VSS EA#
VDD IDD
VDD
P0 EA#
344 ILL F33.3
All other pins disconnected
All other pins disconnected
FIGURE 12-9: IDD TEST CONDITION, ACTIVE MODE
FIGURE 12-11: IDD TEST CONDITION, STANDBY (STOP CLOCK) MODE Note: Idle mode is not supported.
VDD = 3 or 5V VDD P0 RST 8XC5X (NC) XTAL2 XTAL1 VSS EA#
VDD IDD
VDD
344 ILL F25.2
All other pins disconnected
FIGURE 12-10: IDD TEST CONDITION, POWER DOWN MODE
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Data Sheet TABLE 12-11: FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS
Parameter1,2 Reset Setup Time Read-ID Command Width PSEN# Setup Time Address, Command, Data Setup Time Chip-Erase Time Block-Erase Time Sector-Erase Time Program Setup Time Address, Command, Data Hold Byte-Program Time3 Verify Command Delay Time Verify High Order Address Delay Time Verify Low Order Address Delay Time First Burst-Program Byte Burst-Program Time3,4 Burst-Program Recovery4 Burst-Program Time-Out Limit
1. 2. 3. 4.
Symbol TSU TRD TES TADS TCE TBE TSE TPROG TDH TPB TOA TAHA TALA TBUP1 TBUP TBUPRCV TBUPTO
Min 3 1 1.125 0
Max
Units s s s ns
11.7 9.4 1.1 1.2 0 110 50 50 50 85 31 20 45 110 2.3
ms ms ms s ns s ns ns ns s s s s
T12-11.4 344
Time4
Program and Erase times will scale inversely relative to programming clock frequency. All timing measurements are from the 50% of the input to 50% of the output. Each byte must be erased before program. External host mode only.
(c)2002 Silicon Storage Technology, Inc.
S71131-03-000 9/02
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
12.3 Flash Memory Programming Timing Diagrams with External Host Mode
TSU
RST
TES
PSEN# ALE/PROG# EA#
P2[7:6] ,P3[7:6] P3[5:4] ,P2[5:0] ,P1 P0
TRD 0000b 0030H BFH
TRD 0000b 0031H E4H/E2H
344 ILL F02.6
FIGURE 12-12: READ-ID Read chip signature and identification registers at the addressed location.
TSU RST TES PSEN# TADS ALE/PROG# TPROG EA# TCE P3[3] TDH
P3[7:6], P2[7:6]
0001b
344 ILL F03.4
FIGURE 12-13: CHIP-ERASE Erase both flash memory blocks. Security lock is ignored and the security bits are erased too.
(c)2002 Silicon Storage Technology, Inc.
S71131-03-000 9/02
344
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
TSU RST TES
PSEN#
TADS ALE/PROG# TPROG EA# TBE P3[3] TDH
P3[7:6], P2[7:6] P3[5:4], P2[5:0]
1101b AH
344 ILL F04.5
FIGURE 12-14: BLOCK-ERASE Erase one of the flash memory blocks, if the security lock is not activated on that flash memory block. The highest address bits A[15:12] determines which block is erased. For example, if A15 is "0", primary flash memory block is erased. If A[15:12] = "1111b", the secondary block is erased.
TSU RST TES
PSEN#
TADS ALE/PROG# TPROG EA# P3[3] TSE P3[7:6], P2[7:6] P3[5:4], P2[5:0] P1 1011b AH AL
344 ILL F05.4
TDH
FIGURE 12-15: SECTOR-ERASE Erase the addressed sector if the security lock is not activated on that flash memory block.
(c)2002 Silicon Storage Technology, Inc. S71131-03-000 9/02 344
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
TSU RST TES PSEN# TADS ALE/PROG# TPROG EA# P3[3] TPB P3[5:4], P2[5:0] P1 P0 P3[7:6], P2[7:6]
* See Table 4-1 for control signal assignments for PROG-SBx and PROG-RBx.
TDH
AH AL DI 1110b*
344 ILL F06.8
FIGURE 12-16: BYTE-PROGRAM; PROG-SB3, PROG-SB2, PROG-SB1, PROG-RB1, AND PROG-RB0 Program the addressed code byte if the byte location has been successfully erased and not yet programmed. Byte-Program operation is only allowed when the security lock is not activated on that flash memory block.
(c)2002 Silicon Storage Technology, Inc.
S71131-03-000 9/02
344
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
TSU RST TES PSEN# TADS ALE/PROG# TPROG EA# P3[3] TBUP1 row address byte address P0 P3[7:6], P2[7:6] 16K/32K Block 4K Block row address byte address DI 0110b row address = A15: A6; byte address = A5:A0 row address = A15: A5; byte address = A4:A0
344 ILL F07.4
TDH
TDH
TDH
TBUP
TBUP
TBUPRCV
row address byte address DI byte address DI
FIGURE 12-17: BURST-PROGRAM Program the entire addressed row by burst programming each byte sequentially within the row if the byte location has been successfully erased and not yet programmed. This operation is only allowed when the security lock is not activated on that flash memory block.
TSU
RST PSEN# ALE/PROG# EA#
TES
TOA
P3[7:6], P2[7:6]
TAHA
1100b
P0 P1 P3[5:4], P2[5:0]
AL
DO TALA
AH
344 ILL F08.3
FIGURE 12-18: BYTE-VERIFY Read the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block.
(c)2002 Silicon Storage Technology, Inc. S71131-03-000 9/02 344
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
13.0 PRODUCT ORDERING INFORMATION
Device SST89C5x Speed 33 Suffix1 XX Suffix2 XX Package Modifier I = 40 pins J = 44 leads Package Type P = PDIP N = PLCC TQ = TQFP Operation Temperature C = Commercial = 0C to +70C I = Industrial = -40C to +85C Release ID Blank = Initial release A = First enhancement Operating Frequency 33 = 0-33MHz Feature Set and Flash Memory Size 54 = C52 feature set + 16(20) KByte 58 = C52 feature set + 32(36) KByte Note: 4K additional flash can be enabled via VIS bit in SFCF Voltage Range C = 2.7-5.5V Device Family 89 = C51 Core
13.1 Valid Combinations
Valid combinations for SST89C54 SST89C54-33-C-PI SST89C54-33-I-PI SST89C54-33-C-NJ SST89C54-33-I-NJ SST89C54-33-C-TQJ SST89C54-33-I-TQJ
Valid combinations for SST89C58 SST89C58-33-C-PI SST89C58-33-I-PI
Note:
SST89C58-33-C-NJ SST89C58-33-I-NJ
SST89C58-33-C-TQJ SST89C58-33-I-TQJ
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2002 Silicon Storage Technology, Inc.
S71131-03-000 9/02
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
14.0 PACKAGING DIAGRAMS
40
C L
1 Pin #1 Identifier
.065 .075 2.020 2.070 12 4 places
.600 .625 .530 .557
Base Plane Seating Plane
.015 Min.
.220 Max.
.063 .090
.045 .055
.015 .022
.100 BSC
.100 .200
.008 .012 .600 BSC
0 15
Note:
1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .115; SST min is less stringent 2. All linear dimensions are in inches (min/max). 40.pdipPI-ILL.7 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
40-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PI
TOP VIEW
.685 .695 .646 .656
1 44
SIDE VIEW
BOTTOM VIEW
Optional Pin #1 Identifier .042 .048
.020 R. MAX. .042 x45 .056
.147 .158 .025 R. .045
.042 .048 .685 .695 .646 .656 .026 .032
.013 .021 .500 REF. .590 .630
.050 BSC. .020 Min. .026 .032
44.PLCC.NJ-ILL.7
.050 BSC. .165 .180
.100 .112
Note:
1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .650; SST min is less stringent 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
44-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NJ
(c)2002 Silicon Storage Technology, Inc. S71131-03-000 9/02 344
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FlashFlex51 MCU SST89C54 / SST89C58
Data Sheet
Pin #1 Identifier
1
44
34
33
.30 .45 10.00 BSC 12.00 BSC
.80 BSC
11
23
12
10.00 BSC 12.00 BSC
22
.09 .20
.95 1.05 .05 .15 .45 .75 1.00 ref
44.tqfp-TQJ-ILL.6
0- 7
1.2 max.
Note:
1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (0.05) mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.
44-LEAD THIN QUAD FLAT PACK (TQFP) SST PACKAGE CODE: TQJ
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2002 Silicon Storage Technology, Inc. S71131-03-000 9/02 344
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